This page links to a folder that contains three simulated implementations of a subset of the MIPS ISA. These simulations are not intended to show how the MIPS ISA actually is implemented - rather they are intended to familiarize students with various implementation strategies using an ISA they are already familiar with. (I use the MIPS ISA for teaching computer organization and assembly language.) Two of the strategies are similar - but not identical - to actual strategies that have been used in commercial implementations. One is definitely not the way the MIPS ISA is actually implemented.
The package also includes a lab that I use that is based on this simulation.
This simulation shows how the MIPS ISA could be implemented using up to four clock cycles to execute each instruction. Of course, actual MIPS implementations are pipelined, and exhibit behaviors (e.g. delayed branch and delayed load) which this implementation does not. However, for pedagogical purposes understanding this implementation helps the student to understand key concepts before trying to understand a pipelined implementation.
This simulation shows how the MIPS ISA could be implemented using essentially the same microarchitecture as for the multicycle simulation, but broken into four stages, and requiring four clocks to complete most instructions. (A three clock implementation would be possible by using both edges of the clock, but for pedagogical reasons the simplicity of this approach seems preferable.) At any given time, four successive instructions are being executed, one in each stage of the pipeline. As a consequence of the use of pipelining, this simulation exhibits both delayed branch and delayed load.
This simulation shows how the MIPS ISA could be implemented using essentially the same approach as the pipelined implementation, except that it uses interlocking to eliminate data hazards (and thus does not require delayed load though it still requires delayed branch). This is the strategy used for MIPS implementations since the MIPS III ISA. Moreover, for pedagogical purposes, understanding how interlocking can be used can help the student to understand superscalar systems where some form of interlocking is generally required.
No images of this simulation are included here, because the visual appearance is the same as for the pipelined implementation
Last revised October 21, 2009. See change log for history of changes.
